The present technology relates to a storage control apparatus and, more particularly, to a storage control apparatus configured to execute storage control on a memory storing an error detection code along with data, a storage apparatus, an information processing system and a processing method for these storage control apparatus and storage apparatus.
Technologies have been developed in which, in order to increase a storage capacity, a storage (or an auxiliary storage apparatus) is arranged in addition to an information processing system composed of a processor and a work memory (or a main storage apparatus). In such an information processing system, DRAM (Dynamic Random Access Memory) for example is used for the work memory. On the other hand, NVM (Non-Volatile Memory) is sometimes used for a storage. NVM is categorized into the flash memory compatible with the access of large-size data and the nonvolatile random access memory (NVRAM) for high-speed access of small-size data. A typical example of the flash memory is a NAND-type flash memory. On the other hand, typical examples of NVRAM include PCRAM (Phase-Change RAM), MRAM (Magnetoresistive RAM), and ReRAM (Resistance RAM).
It is a general practice, with the nonvolatile memories mentioned above, to execute error detection and correction processing based on ECC (Error Correcting Code) in order to improve the data retention characteristics. To be more specific, at the writing of data, an error correcting code is computed and the computed error correcting code is recorded to a nonvolatile memory along with the data, and, at the time of reading the data, the data and the error correcting code are read at the same time for bit error detection and correction processing. Assuming the error detection and correction processing like this makes it clear that the matching the unit of error correcting code with the unit of access to a nonvolatile memory is advantageous in performance. If no match is found between both the units, the error detection and correction processing based on an error correcting code is executed, so that a portion other than the data requested for access must also be read, thereby increasing the overhead in access processing.
In order to circumvent this problem, a semiconductor storage apparatus is proposed in which two areas of a bank for executing access in the unit of large-size sector and a bank for executing small-size data length access are arranged to execute error detection and correction processing in each size (refer to Japanese Patent Laid-Open No. 2008-084499 below). With this semiconductor storage apparatus, a bank for sequential access in the unit of sector and a bank for random access in the unit of data are arranged in a NAND-type flash memory.